Conventional technologies to configure and manufacture high voltage semiconductor power devices are still confronted with difficulties and limitations to further improve the performances due to different tradeoffs. In vertical semiconductor power devices, there is a tradeoff between the drain to source resistance, i.e., on-state resistance, commonly represented by RdsA (i.e., Rds X Active Area) as a performance characteristic, and the breakdown voltage sustainable by the power device. A commonly recognized relationship between the breakdown voltage (BV) and the RdsA is expressed as: RdsA is directly proportional to BV2.5. For the purpose of reducing the RdsA, an epitaxial layer is formed with a higher dopant concentration. However, a heavily doped epitaxial layer also reduces the breakdown voltage sustainable by the semiconductor power device.
The prior art has described many methods for increasing the BV for power MOSFET devices. Examples of the devices include charge balanced devices such as superjunction MOSFETs and surface enhanced devices with trenches such as a field balance MOSFETs (FBMs).
Superjunctions are a well-known type of semiconductor device. Superjunction transistors provide a way to achieve low RdSA, while maintaining a high off-state BV. Superjunction devices include alternating P-type and N-type doped columns formed in the drift region. In the OFF-state of the MOSFET, the columns completely deplete at relatively low voltage and thus can sustain a high breakdown voltage (the columns deplete laterally, so that the entire p and n columns are depleted). For a superjunction device, the RdSA increases in direct proportion to the BV. This is a much less dramatic increase than in the conventional semiconductor structure. A superjunction device may therefore have significantly lower RdsA than a conventional MOSFET device for the same high BV (or conversely may have a significantly higher BV than a conventional MOSFET for a given RdsA).
Superjunction devices are described, e.g., in “24 mΩcm2 680 V silicon superjunction MOSFET”, Onishi, Y.; Iwamoto, S.; Sato, T.; Nagaoka, T.; Ueno, K.; Fujihira, T., Proceedings of the 14th International Symposium on Power Semiconductor Devices and ICs, 2002, pages: 241-244, the entire contents of which are incorporated herein by reference. FIG. 1A is a cross-sectional view of part of an active cell portion of a conventional superjunction device 100. In this example, the active cell portion of the device 100 includes a vertical FET structure (e.g., an N-channel) formed on a suitably doped (e.g., N+) substrate 102, which acts as a drain region with a drain contact 105. A suitably-doped (e.g., N-Epitaxial (epi) or N-drift) layer 104 is located on top of the substrate 102. In this example, the device 100 also includes a P-body region 106, an N+ source region 108, and an N+ polysilicon gate region 112. The device 100 also includes a gate contact (not shown) and a source metal 114. As seen in FIG. 1A, the superjunction structures may include alternating, charge balanced P-type columns 130 and n-type columns 132. These columns completely deplete horizontally at a low voltage and so are able to withstand a high breakdown voltage in the vertical direction. The N-type columns 132 may comprise of the portions of the n-type epitaxial layer 104 that are situated adjacent to the p-type columns 130.
It is within this context that embodiments of the present invention arise.